1. Field of the Disclosure
This disclosure relates to wafer-level microfabrication methods for micro-electromechanical systems (MEMS) devices. The method can be applied to the fabrication of complementary metal-oxide-semiconductor (CMOS)-MEMS sensors and actuators where electrical isolation of MEMS structures and conditioning circuitry is needed. The method can include an anisotropic etch (e.g., a deep reactive ion etch (DRIE)) from the back-side of a substrate, to create electrical isolation trenches and chip separation trenches; a front-side anisotropic etch (e.g., silicon dioxide in the CMOS layer) to expose silicon sensor structures, and a front-side anisotropic etch (e.g., a substrate DRIE) for MEMS device release. The method avoids the microstructure contamination prevalently existing in other currently available plasma-etch based microfabrication methods that result in structure release failure and, thus, low manufacturing yield.
2. Brief Description of Related Technology
Microfabrication (or micromachining) refers to series of processing techniques used to fabricate devices known as MEMS or micromachined devices (e.g., micromachined inertial sensors such as accelerometers, and other sensors/actuators). MEMS fabrication processes generally involve the sequential addition and removal of layers of materials from a substrate layer using film deposition and etching techniques until a desired structure is obtained. MEMS microfabrication processes largely originate from planar semiconductor processes by which integrated circuits (IC) are manufactured.
Complementary metal-oxide-semiconductor (CMOS)-compatible fabrication processes can be used to create microstructures (or MEMS structures), for example as described in U.S. Pat. Nos. 5,717,631, 5,970,315, 6,458,615, and 7,026,184. Micromachined devices fabricated by CMOS-compatible fabrication processes are attractive because of the ability to integrate high-performance, on-chip signal conditioning circuits with sensing elements, multi-vendor accessibility, and short design cycle times. Such processes can be used to fabricate miniature three-axis accelerometers for use in a variety of applications including automobiles, navigation systems, and medical devices, for example as described in U.S. Pat. No. 7,258,012. CMOS-MEMS processing creates microstructures (e.g., as beams) that are made out of dielectric and metallization layers of CMOS and/or substrate material. One of the CMOS metal layers (or some other layer made from an etch-resistant material) acts as an etch-resistant mask for defining the microstructural side-walls. Reactive-ion etch (RIE) of a CMOS oxide layer creates composite metal/dielectric/substrate material microstructures that can have a favorable aspect ratio (e.g., beam width to beam thickness, gap spacing between adjacent beams to beam thickness). Isotropic etching of the substrate can be performed to electrically isolate portions of the substrate material by removing the substrate material from under a composite micro-structure (e.g., a short, narrow beam). As a result, the substrate material on both sides of the microstructure is electrically isolated but mechanically connected.
Some substantial fabrication limitations have been observed in other CMOS-MEMS processes (e.g., DRIE processes such as those illustrated in references [1-4]). For example, silicon sidewall contamination can be caused by the alternate plasma processing steps performed on the front side of a device die or wafer. The contamination limitation, particularly taking place on the sidewall of electrical isolation trenches, dramatically limits the device release yield. In some cases, additional process steps that are needed to remove the contaminants, can cause the device failure.
Objects
One of the objects of the disclosure is to provide a method for fabricating a micromachined device from a layered wafer including a substrate (e.g., silicon substrate) and one or more composite thin films thereon, in particular where trench and channel structures in the substrate can be formed without etching through the composite thin films from the front side of the device to access/further etch the substrate.
Another object is to eliminate the occurrence of trench sidewall contamination (e.g., metal and polymer contamination such as aluminum and fluorocarbon-based polymers) resulting from a front side etching of the substrate through the composite thin film (e.g., etching through a CMOS thin film layer stack to form trenches in an underlying (silicon) substrate).
Yet another object is to improve the speed and yield of fabrication processes for micromachined devices by eliminating sidewall contamination, reducing the overall number of steps in the process, and facilitating wafer-level device fabrication (e.g., with improved microstructure release and die separation).
These and other objects may become increasingly apparent by reference to the following description.